1. Field of the Invention
This invention relates to the field of wafer processing. In particular, the invention relates to scheduling techniques for wafer cluster tools.
2. Description of the Related Art
In the process of manufacturing a semiconductor device such as an integrated circuit, numerous steps of micro-fabrication are performed to form a device. These steps are performed serially on the individual items of manufacture in individual modules; the items of manufacture are transferred between modules by transport mechanisms such as robots. In order to achieve desirable throughput, reliability, and fabrication quality, several conditions must be met:
1) The delivery and removal of the substrate to and from the process modules, as well as the transportation of the wafer between modules, must be accomplished in a timely manner. This timely delivery and removal of substrate is achieved when the flow of substrate is maintained in a periodic and synchronized manner. If periodicity and synchronization are not maintained, the process results will be inconsistent from substrate to substrate, and the expected throughput may be reduced.
2) It is desirable to transport the substrate in similar process flow paths to avoid inconsistency in process results due to variations in the process history of the substrates.
3) It is imperative to ensure that the articles of manufacture do not spend any pre-process or post-process time idling in modules where critical processes are performed. The addition of pre-process or post-process time in these modules degrades not only the throughput but also the process results. For example, in an IC fabrication system, if a substrate is not immediately transferred from the spin coat module to a bake module to thermally cure a photo-resist film layer, the resulting film thickness will be unpredictable. If it is impossible to totally eliminate pre-process and/or post-process times, they should be rendered as brief as possible, and any variations in these times cannot be allowed.
The inability to meet any or all of the above conditions come from the failure to resolve transport conflicts. Conflicts are situations wherein separate modules demand a robot within a time span insufficient for the robot to service these modules
One conventional solution to the concerns listed above is the addition of extra process modules and transportation resources. However, the size limitations and geometrical constraints of a track system limit the possibility of resolving the above difficulties by adding additional process modules or transportation resources.
The addition of dedicated transfer arms to transfer substrates between adjacent modules (hereinafter called Inter Bay Transfer Arms, or IBTAs) is another method used to improve throughput and eliminate some of the pre-process and/or post-process times. However, the addition of IBTAs also has serious drawbacks. Dedicated transfer arms complicate the tool and increase its cost, constrain the position of the modules, and cannot be used everywhere in the tool. As a result, the tasks of managing the substrate flow in the track system while maintaining both high throughput and quality and resolving all transport conflicts become unmanageable.
Another conventional solution is to assign a set of substrate transport priority rules. Prior to any robot move, the control system, also referred to as the software scheduler, verifies the status of substrates in different modules and makes transfer priority decisions based on these rules. However, to achieve high throughputs, the scheduler may generate undesirable, unpredictable and variable pre-process and post-process times in critical modules, and the substrates may also be forced to follow different flow paths to complete their process cycle.
Heretofore, the requirements of conflict resolution, synchronization, quality, and path consistency referred to above have not been fully met. What is needed is a solution that simultaneously addresses all of these requirements.
An embodiment of the invention allows a cluster tool to change from a first recipe to a second recipe, while preserving periodicity and ensuring that there are no delays at critical points. This procedure is referred to as recipe cascading. Cascading involves emptying a first lot of wafers off a cluster tool and populating the cluster tool with another lot of wafers, serially and simultaneously. The procedure is performed with no delays incurred at critical process steps; and with no additional robots and process modules other than those called for by the recipe and throughput requirements of the entering and the exiting lots. The entering lot may also have different recipe and throughput requirements from the exiting lot.
An embodiment of the invention includes a method for processing wafers which comprises loading a first plurality of wafers into a wafer cluster tool individually at intervals delimited by a first sending period, wherein the first plurality of wafers are processed according to a first recipe; and loading a second plurality of wafers into the cluster tool at intervals delimited by a second sending period, wherein the second plurality of wafers are processed according to a second recipe. In embodiments of the invention, the cluster tool has a transition period, during which the cluster tool processes one or more wafers from the first plurality of wafers according to the first recipe and one or more wafers from the second plurality of wafers according to the second recipe.
Embodiments of the invention also include a computer program for scheduling the wafer processing system. The computer program includes resources for scheduling the wafer processing system during a first time period, wherein a first plurality of wafers is processed during the first time period according to a first recipe; resources for scheduling the wafer processing system during a second time period, wherein a second plurality of wafers is processed during the second time period according to a second recipe; and resources for scheduling the wafer processing system during a third time period, wherein a third plurality of wafers is processed during the third time period, such that one or more wafers from the third plurality are processed according to the first recipe, and one or more wafers from the third plurality are processed according to the second recipe. In embodiments of the invention, the computer program resides on a server coupled to the wafer processing system. In embodiments of the invention, the computer program uses a genetic algorithm to schedule the wafer processing system. In some embodiments, the computer program uses another optimization technique to schedule the wafer processing system.